1. Field of the Invention
The present invention relates to the field of differential low noise amplifiers, LNA. Specifically, the present invention relates to improving input-output isolation in an LNA.
2. Description of the Related Art
The first stage of a high frequency receiver is typically a low-noise amplifier, LNA. The LNA is particularly a key component in wireless communication applications. In such systems, LNAs are used to receive and amplify a signal from an antenna without adding significant noise to the receiver. In addition to amplifying a received signal, typically the LNA is also required to provide a specific input impedance at a prescribed operating frequency. This impedance requirement is particularly important since the impedance quality can greatly affect the performance of passive filters that may precede the LNA. Overall the LNA is one of the most important circuit blocks in a receiver chain for determining the noise performance of the overall receiver chain.
The input impedance requirement places practical limitations on the physical configuration of an LNA-type amplifier. That is, basic (lower frequency) amplifier configurations and techniques may not be suitable for LNA applications. For example, the basic common-source amplifier configuration 9 (shown in FIG. 1) is not suitable for a LNA applications. Common-source amplifier 9 includes an MOS transistor 11 having its source terminal directly coupled to hard ground, GND, its drain coupled to Vcc via a load resistor RL, and its control gate coupled to a signal source 12. Signal source 12 has an inherent output (i.e. source) impedance RS, and outputs an input signal, Vin, to amplifier 9 via source impedance RS. In order to reduce signal reflection and maximize power transfer, amplifier 9 is typically required to provide an input impedance, Rin, that matches source impedance RS. A typical value for RS is 50Ω, and a correspondingly matching input impedance Rin of 50 Ω is likewise typically required at the input of amplifier 9. It is to be understood that this value of 50Ω is purely for illustrative purposes, and any other value for source impedance RS may be defined without deviating from the present discussion.
Nonetheless, a common method of meeting this input impedance requirement is to simply place a matching 50 Ω input resister, i.e. Rin, across the input terminal of common source amplifier 9. This approach is indeed suitable for many lower frequency applications, but it is ill-suited for high frequency applications (i.e. at which LNA-type amplifier are typically used). Input resister Rin adds thermal noise and attenuates a received signal. These two effects generally result in unacceptable noise figures, which make the use of a physical input resistor unsuitable for high-frequency, low-power applications, and thus unsuitable for LNA-type amplifiers.
The active component of an LNA-type amplifier is typically an MOS transistor, whose control gate structure in essence constitutes a parallel plate capacitor. Consequently, the control gate of the MOS transistor exhibits an inherently capacitive input impedance. Therefore, attempting to use the control gate as the input to an MOS transistor to provide an ohmic (not capacitive) input impedance (such as a matching 50Ω input resistance) without adding a physical resistor (to avoid the noise characteristics of physical resistors) may appear to be a futile endeavor. However, MOS transistors have what is termed a nominally capacitive input impedance, and not a purely capacitive input impedance. A physical MOS transistor does exhibit a real input impedance component in addition its capacitive input impedance component. This real impedance component is at least partly due to a finite carrier velocity in the channel (i.e. bottom plate) of an MOS transistor, which results in a bottom plate potential that lags an applied potential at the control gate and thus exhibits a resistive component in its input impedance. Since this lag effect is dependent upon the frequency of an applied input signal, the value of the input ohmic resistance is likewise dependent upon frequency. Nonetheless this phenomena permits an LNA-type amplifier to provide a resistive input impedance without a physical input resistor, within a prescribed operating frequency range.
By increasing this lag effect, an ohmic input impedance without the added noise of a real resistor can be created at the control gate of an MOS transistor. There are several methods for increasing this lag effect in the channel of the transistor, such as simply elongating the channel of the transistor. However, this approach affects the overall performance of the transistor. Generally in an LNA amplifier, inductive source degeneration is used to enhance the lag of current flow in the channel due to an applied input signal. An advantage of this approach is that the real (i.e. ohmic) component of the input impedance can be controlled by selection of an appropriate inductance at the source terminal of the MOS transistor.
This approach is illustrated in FIG. 2, where inductor Ls is added at the source electrode of MOS transistor 11 to provide inductive source degeneration. In this case, the input impedance Zin effectively behaves as a series RLC network with a resistive component proportional to the inductance value of Ls. It should be noted that the input impedance Zin would be purely resistive only at resonance (i.e. where the reactive components of the input impedance cancel out), and thus impedance matching is typically provided for only a narrow frequency range of operation. However, LNA-type amplifiers are typically used in narrow band applications, so this narrow-band operation limitation is typically not critical a hindrance.
With reference to FIG. 3, since inductor Ls provides the desired input resistance only when operating at resonance, a second gate inductor Lg is typically applied at the control gate of transistor 11 to assure that resonance is achieved. That is, the inductance value of Ls necessary for providing a desired input ohmic impedance is first selected. Typically the desired input impedance is selected to match the source resistance Rs of the input signal source 12. The value of Ls needed to produce the desired input resistance, however, may not necessarily be at resonance at the desired operating frequency of the LNA. Since Ls will produce a purely resistive impedance only when the input loop is at resonance, gate inductance Lg is then adjusted to provide enough series inductance with the gate input to push that the input loop into resonance at the desired amplifier operating frequency for the given value of Ls.
With reference to FIG. 4, where all elements similar to those of FIGS. 1–3 have similar reference characters and are described above, a more complete view of a basic LNA structure includes a voltage bias generator 13, a coupling capacitor Cp, and a third inductor Ld coupling the drain electrode of MOS transistor 11 to the Vcc power rail. Voltage bias generator 13 establishes the operating point for the LNA, as determined from power constraints. Coupling capacitor Cp provides DC blocking to prevent disturbance of the gate-to-source biasing of transistor 11. The inductance value of inductor Ld operates in conjunction with the drain capacitance of MOS transistor 11 to increase gain and provide bandpass filtering at the output.
The LNA of FIG. 4 is a single-ended structure, and it is therefore sensitive to parasitic ground inductance. This can be remedied by using a differential LNA structure, as shown in FIG. 5, where all elements similar to those of FIG. 4 have similar reference characters. The differential structure 17 includes a current source 19 that establish a virtual ground 15 at the point of symmetry between the two differential branches.
The differential LNA 17 operates on both true Vin and complement Vin′ forms of an input signal and thus has a true 17a and complementary 17b LNA branch. All elements in the complementary LNA branch 17b that complement those of the true LNA branch 17a have similar reference characters with the addition of prime symbol (′), and their behavior is similar to those of the true LNA branch 17a, as described above in reference to FIGS. 2–4. For simplicity, two input signal sources 12 and 12′ providing two respective input signals Vin and Vin′, along with their corresponding source impedances Rs and Rs′, are shown. It is to be understood, however, that Vin and Vin′ are complements of each other and may originate from a single, distant differential signal source. Similarly, two voltage bias generators 13 and 13′ are shown, but it is to be understood that a single voltage bias generator may be used to bias both the true 17a and complementary 17b branches of differential LNA 17.
Current source 19 isolates virtual ground node 15 from parasitic ground inductances so that the real component of the input impedance is controlled primarily by Ls (or Ls′). An additionally benefits of the differential LNA structure is that it rejects common-mode disturbances as well as improving linearity and dynamic range.
Differential LNA structures began to be used more and more staring in the late 1990's. Use of differential LNA's was driven by the increasing use of the direct conversion receiver (DCR). The DCR topology with differential structures helps improve second order inter-modulation and linearity.
LNA-type amplifiers, however, typically do not have the simplified structures of FIGS. 4 and 5. This is because although the noise figure is not much affected by the gate-to-drain capacitance, Cgd, of MOS transistor 11, Cdg can affect the input impedance. Additionally, the output of an LNA is typically tuned differently than the input, and thus it is helpful to isolate the output form the input. Also it is important prevent leakage from the output signal back to the input stage since the leakage can radiate out through the input stage. For example, an LNA may receive and amplify a signal from an antenna while adding some noise. If its isolation between the input and output is not at a certain level, the signal at the output can go back to the antenna where it can radiate and create interference for other applications or other users of the same application.
With reference to FIG. 6, most low noise amplifiers found in the literature use a cascode topology to reduce the effects of the input transistor's 11 Cgd. In FIG. 6, a single-ended configuration is shown for the sake of clarity, but it is to be understood that the structure of FIG. 6 can be readily extended to a differential LNA structure. The cascode topology replaces the single input transistor 11 with a cascode structure 20 consisting of two transistors, the primary input transistor 11_in in series with a cascode transistor 11csc. The control gate of cascode transistor 11csc is typically tied to the high power supply Vcc to maximize the voltage across input transistor 11_in. The operation of a cascode structure 20 is well known and is not elaborated upon here. In essence, the cascode transistor 11csc reduces the gain of the common-source configuration of input transistor 11_in, and thereby reduces the capacitor multiplying action of the Miller effect upon input transistor 11_in, while at the same time providing isolation between the control gate of input transistor 11_in and the output at the drain of cascode transistor 11csc. Thus, the cascode structure 20 improves the isolation between the input and the output. This implies that an input signal received by an antenna (not shown) and applied to the LNA will ideally have no reflections from the output of the LNA back to the input.
Also shown in FIG. 6 is an example of a typical voltage bias circuit 13. Voltage bias circuit 13 may consist of reference resistor Rref in series with a diode-connected transistor 21, with a bias resistor Rbias coupling the gate of transistor 21 to the gate of input transistor 11_in. The reference current through diode-connected transistor 21 is determined by the value of Rref and the voltage difference between Vcc and the Vgs of transistor 21. Rref is typically made large enough so that its noise current is small enough to be ignored. Transistor 21 essentially forms a current mirror with input transistor 11_in, by which the bias operating point of input transistor 11_in is established.
With reference to FIG. 7, a differential LNA-type amplifier with a cascode structure is shown for the sake of completeness. All elements similar to those of FIG. 6 have similar reference characters and are described above. For the sake of clarity, as in the case of FIG. 5, the bias circuitry and input signals are duplicated for the true and complement branches of the differential LNA, but it is to be understood that a single bias circuit may bias both branches of the differential LNA and the true and complementary input signals may originate from a common differential signal source. Also as in the case of FIG. 5, the complementary components have a prime symbol (′) appended to their corresponding reference character, and are described above. The complementary outputs are therefore available at nodes Out and Out′.
Although the cascode structure reduces the Miller effect and provides isolation between the input and output, and is consequently very popular in LNA architectures, it achieves these benefits at the sacrifice of voltage headroom. That is, the available voltage headroom (i.e. the difference between Vcc and GND as further reduced by voltage drops across any series-connected components between Vcc and GND) for circuit operation is reduced by requiring two transistors 11_in and 11csc in series, as opposed to the single transistor 11 of the basic LNA structure of FIGS. 4 and 5. This means that it will take a smaller Vin signal level to saturate the cascode LNA circuits of FIGS. 6 and 7 as compare to the basic LNA circuits of FIGS. 4 and 5.
Other methods of compensating for, or neutralizing, the Miller effect are known, but are not considered suitable for modern LNA applications. For example, a neutralization technique developed for AM radio broadcast in the 1920's for a single-ended amplifier uses a tapped inductor, or autotransformer, to provide a feedback signal through a capacitor to the input of an active device that is 180° out of phase with the output of the active device. Application of this technique to a non-LNA MOS amplifier is shown in “The Design of CMOS Radio-Frequency Integrate Circuits”, © Cambridge University Press 1998, © Thomas H. Lee 2004, by T. H. Lee, page 296, which is hereby incorporated by reference. But this approach is unsuited for integrated circuit, IC, implementation due to the large area requirements and poor quality of integrated tapped transformers.
A second approach based on a similar principle, but which traditionally has not been broad applicable to integrated circuits, makes use of the dual outputs of a differential amplifier being 180° out of phase to eliminate the need for the autotransformer. This approach is described in “The Design of CMOS Radio-Frequency Integrate Circuits”, © Cambridge University Press 1998, © Thomas H. Lee 2004, by T. H. Lee, pages 296–297, which is hereby incorporated by reference. In this case, the output of one branch of a differential amplifier is coupled to the input the second branch through a capacitor, and vise-versa. In order for this neutralization technique to be applicable to MOS integrated circuits, precise matching of the feedback capacitor with the Cgd of the amplifier transistor is required. However, since the Cgd of an MOS transistor is voltage-dependent (i.e. it varies with an applied potential) precise matching with the feedback capacitor has not been realizable. Therefore, this technique has traditionally had only limited application in semiconductor amplifiers. This difficulty in matching capacitances is particularly important in LNA amplifiers, where a mismatch in the feedback capacitor could set-up a separate resonance through the feedback capacitor leading to instabilities. Consequently, this approach has traditionally been limited to vacuum tube technology, which have highly linear and relatively constant coupling capacitances.
What is needed, therefore, is a method of isolating the input and output of an integrated MOS LNA circuit without losing additional voltage headroom, as compared to the basic MOS LNA circuit.